ESD launched its CAN-USB/400, which is based on the company’s Advanced CAN core (ACC) implemented in an FPGA by Altera.
The USB dongle uses the same esdACC as the other CAN FD interface products by the company located in Hanover, Germany. The FPGA hosts the two CAN FD cores and provides advanced diagnostic features as well as high-resolution time-stamping of received and transmitted messages. This includes the possibility to inject errors. Bit pattern can be injected into the CAN network, in order to test the reaction of the other nodes. Several trigger conditions and modes are provided. The time-stamping was explained in detail in a paper presented at the iCC 2017. The device internal architecture features FIFO’s to connect the FPGA to the USB interfaces. According to the provider, the product is designed for minimum latency CAN communication via USB.
The product comes with an operating system (OS) independent API (application programming interface). A software driver is available for Windows; other OSs are supported on request. For Windows, the supplier offers several higher-layer protocol stacks (Arinc 825, CANopen, and J1939), They support only Classical CAN. Specifications for CAN FD support are not yet finalized by CiA and approved by SAE.
The shown PCIe board was the first CAN FD product using the above-mentioned esdACC. The on-board termination resistors can be enabled and disabled. The up to two CAN FD interfaces support bit-rates from 10 kbit/s to 5 Mbit/s using the very same transceiver. The CAN FD ports are galvanic-isolated. Software support is provided for Windows, Linux, QNX, RTX, RTX64, and others.
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