CAN FD core
Fraunhofer’s IPMS_CAN is a CAN controller that performs serial communication according to Classical CAN and the CAN FD specification. It is compatible to ISO CAN FD and the non-ISO (Bosch) CAN FD standard.
THE CAN PROTOCOL USES A MULTI-MASTER BUS CONFIGURATION for the transfer of frames between nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up links between various components. It appears as a memory-mapped I/O device to the host processor, which accesses the IPMS_CAN core to control the transmission and reception of frames.
The core offers a generic processor interface or optionally an AMBA AHB or APB interface. It provides programmable interrupts, data and bit-rates, as well as a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to the requirements of each specific application. The number of receive buffers is synthesis-time configurable from 2 to 64. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable from 0 to 16 slots. Moreover, an optional wrapper instantiating multiple CAN controller cores eases the integration in cases where multiple bus-nodes need to be controlled by the same host processor.
The core implements functionality similar to the Philips SJA1000, working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features. Beside compatibility to Classical CAN, the core offers compatibility to the CAN FD extension (ISO and non-ISO) to increase the data throughput. It comprises data fields up to 64 bytes, extended CRC checksum, and a higher data rate for the payload.
The IPMS_CAN core can be integrated in devices that use CAN or higher-layer CAN- based communication protocols. In addition to traditional automotive applications, such devices are used in industrial (e.g. the CANopen and Devicenet protocols), aviation (e.g. the ARINC-825 and CANaerospace protocols), marine (e.g. the NMEA 2000 protocol), and other applications.
The core is able to switch between ISO CAN FD and non-ISO CAN FD during runtime. With the CAN FD data rate, an extended data field with up to 64 bytes is possible. The error analysis enables diagnostics, system maintenance, and system optimization, while the listen-only mode enables CAN traffic analysis and automatic bit-rate detection. Two clock domains for the CAN protocol machine and host controller interface enable the usage of an optimal clock for CAN communication independent from the host clock.
The number of independently programmable 29-bit acceptance filters is configurable from 1 to 16. Optional memory protection using ECC is available. The data rate is programmable up to 1 Mbit/s with Classical CAN and several Mbit/s with the CAN FD option. The bit-rate prescaler is also programmable, from 1/2 up to 1/256. The single shot transmission mode enables a lower software overhead and fast reloading of transmit buffer. Buffers can be implemented as Flip-Flops or RAM, and a single host can control multiple CAN nodes via an optional Multi-CAN wrapper. The core is available in RTL, and portable to ASIC and FPGA technologies. It has the size of approximately 30000 gates.
The core has been tested by a Bosch reference model and has been production proven multiple times, according to Fraunhofer. It includes everything required for successful implementation: a VHDL or Verilog RTL source code, a post-synthesis netlist for FPGA, test benches (behavioral, post-synthesis verification), simulation scripts, synthesis scripts, and documentation. The core is available from Cast (US).
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