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CAN FD IP core

Silvaco and NXP collaborate

Silvaco (USA) has expanded its portfolio of IP cores with the addition of FlexCAN, a CAN controller compliant with ISO 11898:2015. It supports the CAN FD protocol.

The mailboxes are configurable to store 0 to 8, 16, 32, or 64 data byte (Photo: Silvaco)
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FlexCAN is part of the company’s IPextreme portfolio of IP cores developed in conjunction with semiconductor companies. The IP core supports the Classical CAN as well as the CAN FD protocol. It also offers backward compatibility, improved performance, and a proven silicon heritage from Freescale (now: NXP).

Silvaco recently entered the semiconductor IP market with the acquisition of IPextreme. The reviewed FlexCAN core was developed in conjunction with NXP. "The FlexCAN core builds upon our successful relationship with NXP and is an important addition to our large portfolio of proven technology created as a result of this partnership", said Warren Savage, General Manager of the IP Division at Silvaco, "The market demand for faster CAN technology is expanding quickly. The availability of our FlexCAN core allows customers to share the benefits from NXP’s years of experience in the automotive semiconductor sector, meeting the stringent requirements necessary for success in this market."

The Californian company headquartered in Santa Clara is an EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. For over 30 years, Silvaco has enabled its customers to bring products to market at reduced cost and in the shortest time.

The FlexCAN core comes with a Verilog RTL source code, a test bench, and documentation. The transmit- and receive-mailboxes are configurable (0 to 8, 16, 32, or 64 byte). The receive FIFO is able to store up to 6 data frames. The time-stamping is based on a 16-bit free-running timer with an optional external time tick. The transmission of data frames can be aborted. The core features listen-only mode and CAN FD transmitter delay compensation. Additionally, it provides a detection and correction (ECC) of memory read.

hz



Publish date
2016-07-05
Company

NXP
Silvaco

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