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CAN FD core

IP core with 8-bit host interface

Xilinx provides the CAN-CTRL core for its FPGA families supporting Classical CAN and CAN FD. Optionally, it features an AMBA-APB interface for ARM-based host controllers.

The CAN FD Logicore IP core is suitable for different FPGA families (Photo: Xilinx)

The US-company offers a Logicore IP core that complies with ISO 11898-1:2015. It features programmable interrupts and a configurable number of independently programmable acceptance filters. Of course, the bit-rates for arbitration phase and dataphase are configurable, too. The bit-rate prescaler is programmable from 1/2 to 1/256. Besides the generic 8-bit host controller interface, an AMBA-APB interface is optionally available. The core can be integrated in the company’s FPGA products (e. g. Zynq-7000, Virtex-7, Kintex-7 Spartan-6, Virtex-6, Virtex-5, and Spartan-3). The Vivado Design Suite supports the core integration into FPGAs.

The CAN module implements a flexible buffering scheme, allowing fine-tuning of the core size to the requirements of the application. The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable from 0 to 16 slots. The number of receive buffer is configurable (2 to 31).

Moreover, an optional wrapper instantiating multiple CAN cores eases integration in cases where multiple bus-nodes need to be controlled by the same host processor. The core implements functionality similar to NXP’s SJA1000 working with its PeliCAN mode extensions.


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