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Dual-core MCU

Radiation-tolerant processor with two CAN ports

Cobham Gaisler has developed the GR712RC processor. It has been launched onboard the SpaceIL mission to the moon.

The GR12RC features two on-chip Classical CAN modules (Photo: Cobham Gaisler)

The SpaceIL mission is an Israeli non-profit organization assisted by Israel Aerospace Industries (IAI). It has constructed the Beresheet lunar lander and launched it atop a SpaceX Falcon 9 rocket from Cape Canaveral Air Force Station on 21 February, 2019. The GR712RC dual-core processor is employed in the Beresheet mission computer and manages all aspects of the journey and landing. The processor is based on Cobham Gaisler’s Sparc-based space-ready processor cores and on Ramon Chips’ radiation-tolerant silicon technology.

“Ramon Chips developed its Radsafe high-reliability silicon technology and applied it in the design of the GR712RC radiation-tolerant processor with demanding missions like Beresheet in mind,” said Prof. Ran Ginosar, CEO of Ramon Chips. “SpaceIL’s young entrepreneurs were early adopters of the GR712RC processor and wrote software for it even before the silicon existed. We are confident that this achievement will lead to many more successful space enterprises benefiting from GR712RC.”

“Cobham congratulates the SpaceIL and IAI teams for the successful launch of the Beresheet lunar lander and wish them a successful landing on the Moon”, said Sandi Habinc from Cobham Gaisler. "The GR712RC enables a high-level of system integration by providing a multitude of interfaces. This, combined with the high computational power of two processor cores, makes it an attractive system-on-chip device with low power consumption that is easy to integrate in spacecraft platform and payload. Close collaboration with Ramon Chips during the GR712RC development resulted in an excellent product, now accepted world-wide as the solution of choice for many space missions.”

“The GR712RC processor forms the heart of the Beresheet onboard computer, providing the required processing power and interfaces to the other spacecraft subsystems, reducing the weight and power consumption that are both critical to this type of mission, while also providing the necessary reliability. All in one chip,” said Opher Doron, VP, General Manager Space Division, Israel Aerospace Industries. “These characteristics greatly simplified the design of the onboard computer and also of the surrounding subsystems on the lander.”

“When we started writing our application software, the GR712RC did not even exist. But the beauty of Cobham Gaisler owning and fully understanding their processor technology, is that they can offer very accurate prototypes and simulators to early adopters, allowing them to be productive with their software development right from the start,” said Dr. Ido Anteby CEO of SpaceIL. “This allowed us to get a head start with developing what is the most important aspect of any computer application, the actual software, without needing to worry that the final flight hardware would differ and invalidate our development efforts.”

The dual-core processor is fabricated at Tower Semiconductors using a 180-nm CMOS technology. It employs radiation-hardened by-design methods from Cobham Gaisler and the Radsafe technology from Ramon Chips. The Sparc V8-based MCU provides several communications interfaces including CAN. It also brings cost reductions to software development since the core functionality can be reused from application to application, only changing the driver software for the interfaces.

The processor features hardware support for cache coherency, processor enumeration, and interrupt steering. Each processor core includes a Sparc Reference Memory Management Unit (SRMMU) and an IEEE-754 compliant double-precision FPU for floating-point operations. It can be utilized in symmetric or asymmetric multiprocessing mode.


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Cobham Gaisler
Ramon Chips
Tower Semiconductor