CAN (FD) IP core
Digital Core Design (DCD) provides the DCAN FD IP core for implementation of standalone CAN (FD) controllers. The company’s subsidiary DCD-Semi also offers the CAN-All ecosystem considering automotive safety standards.
DCAN FD is dedicated for implementation of standalone Classical CAN and CAN FD controllers according to ISO 11898-1:2015. It is provided as HDL (hardware description language) source code, allowing target use in FPGA (field-programmable gate arrays) and ASIC (application-specific integrated circuit) technologies. It enables the use of 11-bit and 29-bit CAN-Identifiers and bit rates of up to 8 Mbit/s, informs the Polish company. It also supports the CANopen FD stack by Emotas.
The core has a CPU (central processing unit) interface configurable for 8-bit, 16-bit, or 32-bit data width and using little- or big-endian addressing scheme. Hardware message filtering and a 128-byte receive FIFO (first in first out) enable back-to-back message reception, with minimum CPU load. The integrated baud-rate prescaler (BRP) defines the length of a time quantum. The bit timing logic (BTL) processes the bit time, calculates position of the sample point, and performs synchronization. For fault confinement handling, the error management logic (EML) is responsible. The acceptance filter (ACF) decides, whether incoming messages are accepted or not, based on filter registers settings. The Tx/Rx RAM interfaces to external dual-port memories are used by the core, to store received and transmitted frames.
The company provides the Verilog or the VHDL source code and test bench environment as well as the required technical documentation. Technical support includes the IP core implementation, design consulting, a 12-months maintenance, documentation updates, and support via phone and email. Offered licensing methods include the One-Site license dedicated to small and middle-sized companies, which run their business at one place. The Multi-Site license option is dedicated to corporate customers, which operate at several locations. The number of IP core instantiations within a project, the number of manufactured chips, and the time of use are not limited.
Digital Core Design is an IP core provider and a system-on-chip design house. The company was founded in 1999 and since the beginning has been focused on IP core architecture improvements. The company’s silicon-proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies such as Intel, Siemens, Philips, General Electric, Sony, and Toyota.
The CAN-All ecosystem by DCD-Semi implements a CAN controller for Classical CAN, CAN FD, and, soon, CAN XL networks, announced the company. It is available in basic or safety-enhanced versions. The CAN-All core features programmable interrupts, data, and bit rates, a configurable number of independently programmable acceptance filters, and a generic processor interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.
The safety-enhanced solution has been developed as ISO-26262-10 safety element out of context. It can optionally be improved by necessary safety mechanisms (e.g. failure detection and system-level safety analysis) and provide detailed safety documentation. Available step-by-step instruction should help to integrate the IP into the customer’s system. All the safety-related work products were checked by a third-party, independent audit. The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the ASIL-B (automotive safety integrity level). The manufacturer can also optionally deliver higher ASIL-level-ready IP.
CAN-All is already proven in several events and production designs. The verification is based on more than two decades of market experience and thousands of automotive implementations with such companies as Volkswagen and Toyota.
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