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CAN SIC transceiver

Provides standby mode

NXP offers the TJA1462 CAN SIC transceiver intended as a replacement for CAN high-speed transceivers, such as the TJA1042 or TJA1044GT. It features a low-power, standby mode.

The 8-pin CAN SIC transceiver is available in different housings (Source: NXP)

The TJA1462 is a member of the TJA146x family of transceivers suitable for Classical CAN as well as CAN FD networks. It complies with the ISO 11898-2:2016 standard and the SAE J2284-1 to SAE J2284-5 specification. Additionally, it meets the signal improvement capability (SIC) requirements of CiA 601-4. The SIC function reduces signal ringing in a network, allowing reliable CAN FD communication to function in larger topologies. In addition, the TJA1462 features a much tighter bit timing symmetry performance to enable CAN FD communication up to 8 Mbit/s, stated the manufacturer.

The TJA1462 is intended as a simple replacement for high-speed Classical CAN and CAN FD transceivers, such as the TJA1042 or TJA1044GT from NXP. It offers pin-compatibility and is designed to avoid changes to hardware and software design, allowing the TJA1462 to be retrofitted to existing applications. An AEC‑Q100 Grade 0 variant, the TJR1462, is available for high-temperature applications, supporting operation at +150 °C ambient temperature.

The CAN SIC transceiver comes in two variants, each available in an SO8 or HVSON8 package. The TJA1462A is a CAN HS (high-speed) transceiver with normal and standby modes and a VIO supply pin. The VIO pin allows for direct interfacing with 3,3‑V and 5‑V micro-controllers. The TJA1462B is suitable only for 5-V operation.

The offered transceivers can detect undervoltage with defined handling on all supply pins. Functionality is guaranteed from the undervoltage detection thresholds up to the maximum limiting voltage values. There is also a defined behavior below the undervoltage detection thresholds. The transceiver disengages from the network (high-ohmic) when the supply voltage drops below the off-mode threshold. The internal biasing of TXD and mode selection input pins enable a defined fail-safe behavior. The network pins are protected against transients and features an ESD (electrostatic discharge) handling capability (6-kV IEC and 8-kV HBM). The chip is protected against over-temperature and provides a TXD dominant time-out function.

hz

Publish date
2022-04-26
Company

NXP

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