The Delfino TMS320F2837xD by Texas Instruments (USA) is a dual-core micro-controller with integrated analog features and communications interfaces. The dual real-time control subsystems are based on the company’s 32-bit TMS320C28x Floating-Point CPUs and feature two control law accelerators (CLAs).
Functional diagram of the micro-controller (Photo: TI)
THE TWO ACCELERATORS ENABLE APPLICATIONS that require parallel control algorithms. Designers can realize up to 800 MIPS of total system performance. The series introduces the trigonometric math unit, which is an accelerator that reduces the number of cycles required to perform common trigonometric functions. The device also has a second-generation Viterbi Complex Math Unit with improved acceleration on Viterbi operations, complex multiplies, and the CRC engine.
Connectivity peripherals such as dual external memory interfaces, dual CAN interfaces, and a Universal Parallel Port (uPP) are available. The uPP is a high-speed, parallel data bus that allows direct connection to FPGAs or other devices with similar interfaces. A USB 2.0 OTG port with MAC and PHY lets users add USB connectivity to their application.
The CAN module operates in a loopback mode receiving its own message (Photo: TI)
The CAN module supports data rates up to 1 Mbit/s and has 32 mailboxes. It features a low-power mode, programmable wake-up on bus activity, automatic reply to a remote request message, automatic retransmission of a frame in case of loss of arbitration or error, 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16), and a self-test mode. A "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit.
The micro-controller supports up to 1 MiB of ECC-protected on-board flash memory and up to 204 KiB of SRAM with parity. Two independent security zones are also available for 128-bit code protection. High-precision control peripherals such as Enhanced Pulse Width modulators with fault protection, encoders, and captures are also included. The analog subsystem boasts up to four 16-bit analog-to-digital converters, as well as eight comparator subsystems. Each comparator subsystem contains two comparators and a built-in 12-bit DAC reference. Each comparator subsystem can be used as peak-current-mode comparators or as windowed comparators. In addition, the device has three 12-bit digital-to-analog converters.
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