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Camera

Freely programmable FPGA

The Razer-Cam by EVT (Germany) is a camera with integrated freely programmable field-programmable gate array (FPGA), which allows data to be preprocessed in real time. It provides a CAN network.

The camera’s system is equipped with a CAN network (Photo: EVT)

DUE TO THE FACT that most of the FPGA are available for the user, even complex applications such as e.g. contour matching can be processed directly. Based on the Xilinx Zynq SoC architecture, the camera is equipped with two ARM cores. The Razer-Cam series is available in three sensor options. The user can choose between two matrix sensors. The system is equipped with an Ethernet interface as well as a CAN network or EIA-485 interface and digital I/Os. Therefore the camera can be embedded directly into process environments.

The camera is equipped with a Linux operating system. The user can therefore start programming with the standard tools for Linux. An extensive API helps to create individual programs in C++ or C code. Because of the numerous libraries for the ARM processor cores, applications can be solved. As the FPGA allows the processing of image data during image capture, the camera is suitable for high-speed tasks, where the data has to be preprocessed. The programming of the FPGA is possible via various tools. On the one hand with VHDL and on the other hand with a graphical GUI, where ready-made functional blocks are arranged and compiled.

A tool chain, which allows programming in C/C++, is included and pre-configured. Optionally a directly executable image for a virtual machine is also included. The programming systems are available for Windows and Linux programming environments, for native as well as virtual machines.

The product is also available as the so-called Eye-Check 4xxx with integrated Eye-Vision software. As already known from other Eye-Vision systems, the inspection programs of the Eye-Check 4xxx can be created within the graphical user interface via drag-and-drop programming. Optionally the programming of the FPGA can be done via graphical tools.



Publish date
2014-06-26
Company

EVT
Xilinx

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