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Simulating and analyzing

For verification of CAN XL implementations

The CAN XL Verification IP by Smartdv is compliant with the CiA 610-1 and CiA 611-1 specifications as well as according conformance test plans (CiA 610-2 and CiA 611-2), claimed the provider.

CAN XL Verification IP topology (Source: Smartdv)

The CAN XL Verification IP includes a test suite covering most of the possible scenarios and CAN XL conformance specifications, informed the company. It can perform the defined protocol tests as a testbench and allows generation of variety of patterns (including a set of specified patterns) to stress the DUT (device under test).

The IP runs in such simulation environments as Systemverilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, Vera, Specman E, and further. It comes with an optional GUI-based Smart Vipdebug visual protocol debugger, which enables to speed up the debugging process. It supports the specified CAN XL frame types and types of error insertion and detection (e.g. bit error, stuff error, CRC error, form error, ACK error, PCRC error). It also tracks the TEC/REC error counter and fault states and allows glitch insertion and detection. The tool monitors, detects, and notifies the testbench of significant events such as transactions, warnings, timing, and protocol violations. Status counters for various events on the network are available. Callbacks in transmitter and receiver nodes allow monitoring of the user processing data. Re-transmission of corrupted messages is implemented.

The manufacturer added that the use of the tool enables faster testbench development and verification of CAN XL designs and simplifies the analysis of testing results. Available examples show how to connect various components, and the usage of transmitter, receiver, and monitoring functions. Detailed documentation of all classes, tasks, and functions used in verification environment is available. Documentation also contains user's guide and release notes.

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Publish date
2022-09-28
Company

Smartdv

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